The design and manufacture of (telecommunication) signal processing circuits implemented by the use of integrated circuit technology is typically limited by absolute device characteristics, which are ordinarily not well controlled, due to processing variations among different wafer batches. In an effort to circumvent this limitation, integrated circuit designers may take advantage of the ability to match multiple like devices on the same chip, which results in several orders of magnitude of reduction in the variation of characteristics of absolute devices resident in wafers obtained during separate processing runs. Namely, by designing circuit architectures whose critical parameters depend only upon on-chip device matching, such circuits can be made to be effectively insensitive to absolute device characteristics.
One type of circuit that takes advantage of such device matching on a single chip is a sampled data circuit, such as that used to construct highly accurate (telecommunication signal processing) filters, whose corner frequencies are dependent upon device matching, rather than absolute device parameters. However, a shortcoming of such sampled data filter circuits is the fact that their use is limited to low bandwidth applications (below a few hundred kilohertz), since parasitic components (capacitances) limit their maximum operating frequency. At higher frequencies it becomes necessary to use continuous time techniques, such as g.sub.m /C and MOSFET/C architectures, or other tunable R/C filter mechanisms in order to avoid the parasitic problem.
One example of a continuous time circuit that is commonly employed in high frequency filters is diagrammatically illustrated in FIG. 1, and comprises an integrator stage 10 formed of a combination of a transconductance (g.sub.m) stage 11 and a load element, in particular an integrating capacitor (C.sub.L) 13. The transconductance (g.sub.m) stage 11 contains a transconductance element which produces an output current I.sub.gm, that is proportional to a voltage Vin applied to input terminal 12. With the output current I.sub.gm of transconductance stage 11 being applied to an output terminal 14, to which the load capacitor (C.sub.L) 13 is coupled and from which an output voltage Vout is derived, then the transfer function of the integrator stage 10 of FIG. 1 may defined by the equation: EQU Vout/Vin=g.sub.m /sC.sub.L. (1)
By connecting two of the integrator stages of FIG. 1 in cascade, as diagrammatically illustrated in FIG. 2, a simple first-order low-pass filter may be realized. As shown therein, first and second transconductance stages 11-1 and 11-2 are coupled in cascaded between an input terminal 12 and output terminal 14. The respective output currents I.sub.gm1 and I.sub.gm2 produced by stages 11-1 and 11-2 are summed at output terminal 14, so that the overall transfer function of the low-pass filter of FIG. 2 may be defined by the equation: EQU Vout/Vin=(g.sub.m1 /g.sub.m2)*(1/(1+sC.sub.L /g.sub.m2). (2)
From equation (2) it can be seen that the pole frequency is process-dependent, since it is determined by the ratio of the process-dependent terms: g.sub.m2 /C.sub.L. It is not atypical for the absolute accuracy of either process-dependent term to vary on the order of +/-20% over all process and temperature extremes. Since, in most cases, such a variation in the filter's corner frequency is unacceptable, on-chip compensation is necessary, in order to force the transconductance-to-capacitance ratio to fall within predetermined limits. Such compensation is ordinarily provided by means of an auxiliary phase-lock loop, with g.sub.m being tuned so as to lock a g.sub.m -controlled master local oscillator to a reference frequency with a g.sub.m -based control voltage being employed to drive a slave g.sub.m stage. This tuning scheme used sets g.sub.m *C of slave filter stages, such that the corner frequency of the filter is at the desired value. For a description of an example of such a tuning circuit, attention may be directed to the article by F. Krummenacher et al, entitled: "A 4 MHz CMOS Continuous-Time Filter with On-Chip Automatic Tuning," IEEE Journal of Solid-State Circuits, VOL. 23, NO. 3, Jun., 1988, pp 750-758. Unfortunately, dedicating such a phase-locked loop tuning circuit for processing variation compensation adds considerable additional semiconductor real estate and circuit complexity, thereby increasing circuit cost.
FIG. 3 diagrammatically illustrates one proposed alternative transconductance control circuit configuration, described in an article by C. Laber et al, entitled: "A 20 MHz Sixth Order BiCMOS Parasitic-Insensitive Continuous-Time Filter and Second Order Equalizer for Disk-Drive Read Channels," IEEE Journal of Solid State Circuits, Vol. SC-28, pp 462-470, April 1993, which makes it possible to tune g.sub.m by means of a very precise control mechanism that is independent of chip processing parameters. The Laber et al control mechanism involves the use of a precisely controllable external resistor Rext, the value of which is effectively translated to a reference resistor within the circuit, that sets the operational parameters of the transconductance stage, such that the transconductance g.sub.m is defined by n/Rext, where n is a scaling factor established by a current feedback loop.
More particularly, the transconductance control circuit of FIG. 3 comprises a first current source 21, which is coupled in circuit with an external reference resistor 23 between first and second DC voltage supply terminals 25 and 27. The first current source 21 is operative to generate a current having a value of .delta.I, and the value of external reference resistor 23 is denoted as Rext. Thus, the voltage at node 26 of external reference resistor 23 is .delta.I*Rext.
Node 26 of external resistor 23 is coupled to a first input 31 of an operational amplifier 30, the output 33 of which is coupled to the control gate 35 of a MOSFET 36. MOSFET 36 has its source-drain current flow path coupled in circuit with a current mirror circuit 40 and an internal reference resistor 43, having a resistance value Rint, which is coupled between a node 45 and the DC voltage supply terminal 27. Node 45 is coupled in a feedback path to a second input 32 of operational amplifier 30. As a consequence, the voltage delta .delta.I*Rext across the external resistor 23 is effectively transferred across internal reference resistor 43, so that the current I.sub.Rint through internal reference resistor 43 is .delta.I*Rext/Rint.
Current mirror circuit 40 replicates the current I.sub.Rint through a circuit path containing a pair of series-connected resistors 51 and 52, the value of each of which is set equal to half the value of resistor 43, namely Rint/2. The node 53 between resistors 51 and 52 is coupled to a first input 54 of an operational amplifier 60, a second input 55 of which is coupled to receive a reference voltage Vcm. The output 57 of amplifier 60 is coupled to the control gate of MOSFET 62, which has its source-drain path coupled in circuit with series connected resistors 51 and 52 and voltage supply terminal 27. Resistors 51 and 52 are coupled to respective inputs 63 and 65 of a transconductance stage 68. Transconductance stage 68 has its output 69 coupled to an output node 71, which is coupled via link 73 to a g.sub.m adjustment input 75 of stage 68 and to a current generator 80. Current generator 80 is operative to apply a current .delta.I*n, where n is a scaling factor, to a current mirror control loop 81.
in operation, with the resistance value Rext of external resistor 23 being translated to internal reference resistor 43, current mirror 40 applies a current .delta.I*Rext/Rint through the path containing series-connected input resistors 51 and 52 of transconductance stage 68. As a result, the input voltage applied to transconductance stage 68 is (.delta.I*Rext/Rint) * (Rint/2+Rint/2) or .delta.I*Rext. The output current generated by transconductance stage 68 is therefore g.sub.m68 * .delta.I*Rext. Because of the current feedback loop provided by current generator 80, the output current of transconductance stage 68 is forced to be equal to .delta.I*Rext*n, so that g.sub.m68 is forced to be equal to n/Rext. In other words, the external resistance transfer and current mirror feedback mechanisms of the circuit of FIG. 3 enables the transconductance g.sub.m68 of stage 68 to be readily established by means of a well defined external resistance value Rext (multiplied by a prescribed scaling factor n), so that one component (the g.sub.m component) of the dual variable integrator stage described above with reference to FIG. 1 can be precisely controlled, independent of processing parameters of the components of the transconductance stage.
However, since the remaining component--the integrating (load) capacitor C--is subject to processing parameter variations, the overall behavior of the filter circuit is still dependent upon such processing variations, so that, as noted above, the corner frequency may shift by as much as twenty percent in extreme cases.